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Dr Haissam ZIADE .

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Professeur (cadré), Université Libanaise, Faculté de Génie.
Docteur et Ingénieur en Automatique, I.N.S.A., France.

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N.B.
This webpage text is not from Dr Haissam ZIADE
All this webpage and text is from the WebMaster.

Exemples de Cours donnés par Dr H. Ziadé au D.E.A. Contrôle industriel,
Diplôme d'Etudes Approfondies, Faculté de Génie, Université Libanaise

  • TCE3 - Processeurs, opérateurs spéciaux

  • ...


Exemples de Publications Scientifiques ...

  • ANNIE 2004
    Architectures III,
    MP2.1B
    "An Efficient and Fault Tolerant Algorithm for Multilayer Neural Network"
    Rafic A. Ayoubi, University of Balamand, Tripoli Lebanon
    Haissam A. Ziade, Lebanese University , Tripoli Lebanon
    Magdy Bayoumi, University of Louisiana, Lafayette, LA

  • ICTTA 2004
    SEN13: Internet applications & performances
    Co-Chairs: Pr. Haissam Ziade, Lebanese University, Tripoli Lebanon, [...]
    http://ictta.enst-bretagne.fr/2004/finalsessions/FINAL_Sessions.pdf

  • ICTTA 2004
    SEN13: Internet applications & performances
    "A Program for Opinion Survey in Arabic for Servicing the Media and Researchers in the Middle East"
    H. Ziade, M. Hayek, Y. Lakys, Lebanese University, Tripoli Lebanon
    Al-Wali, AFAAQ Company, Tripoli Lebanon
    F. Ziade, Faculty of Public Health, Lebanese University, Tripoli Lebanon

  • ICTTA 2004
    SEN13: Internet applications & performances
    "Are we really protected against hackers?"
    S. Baroudi, H. Ziade, Lebanese University, Tripoli Lebanon
    B. Mounla, CDC Technologies, Beirut Lebanon

  • Defect and Fault Tolerance in VLSI Systems 2004
    "Fault Tolerant Hopfield Associative Memory on Torus"
    Rafic Ayoubi, Haissam Ziade, Magdy Bayoumi
    Abstract: The associative Hopfield memory is a very useful Artificial Neural Network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an efficient and fault tolerant algorithm for implementing the Hopfield ANN on torus parallel architecture. The main advantage of this algorithm is fault tolerance, high performance, and cost effectiveness. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube without the added cost; it requires O(1) multiplications and O(log N) additions, whereas most others require O(N)multiplications and O(N) additions. Moreover, the developed algorithm has an added advantage over other known algorithms due to its fault tolerance feature, which is based on ABFT techniques. The main advantage of our ABFT method over other existing ABFT methods is its ability to detect and correct several faults without any additional hardware overhead (i.e. no extra row or column is needed).

  • IEEE International Symposium on Circuits and Systems (ISCAS)
    ISCAS 2004, Vancouver, British Columbia, Canada
    Technical Program
    Paper: NSA-P2.5
    Session: Neural Network Circuits and Systems II
    Topic: Neural Systems and Applications: Neural Network Architectures and Algorithms
    "HOPFIELD ASSOCIATIVE MEMORY ON MESH"
    Rafic Ayoubi, University of Balamand
    Haissam Ziade, Lebanese University
    Magdy Bayoumi, University of Louisiana
    Abstract:The associative Hopfield memory is a very useful Artificial Neural Network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an algorithm for implementing the Hopfield ANN on mesh parallel architectures. A Hopfield ANN model involves two major operations; broadcasting a value to a set of processors and summation of values in a set of processors. The main advantage of this algorithm is high performance and cost effectiveness. An iteration of an N-bit (neuron) Hopfield associative memory only requires O(log N) time, whereas other known algorithms in literature of similar topology require O(N) time. Moreover, the proposed algorithm is cost effective because only higher dimension architectures were reported to achieve a complexity of O(log N) such as hypercubes.

  • The International Arab Journal of Information Technology
    July 2004, Volume 1, Number 2
    "A Survey on Fault Injection Techniques"
    Haissam Ziade, Faculty of Engineering I, Lebanese University, Lebanon
    Rafic Ayoubi, Faculty of Engineering, University of Balamand, Lebanon
    Raoul Velazco, IMAG Institute, TIMA Laboratory, France
    Abstract: Fault tolerant circuits are currently required in several major application sectors. Besides and in complement to other possible approaches such as proving or analytical modeling whose applicability and accuracy are significantly restricted in the case of complex fault tolerant systems, fault-injection has been recognized to be particularly attractive and valuable. Fault injection provides a method of assessing the dependability of a system under test. It involves inserting faults into a system and monitoring the system to determine its behavior in response to a fault. Several fault injection techniques have been proposed and practically experimented. They can be grouped into hardware-based fault injection, software-based fault injection, simulation-based fault
    injection, emulation-based fault injection and hybrid fault injection. This paper presents a survey on fault injection techniques with comparison of the different injection techniques and an overview on the different tools.
    Keywords: Fault tolerance, fault injection, fault simulation, VLSI circuits, fault injector, VHDL fault models.
    Received May 19, 2003; accepted October 13, 2003.

  • The International Arab Journal of Information Technology
    "A Survey on Fault Injection Techniques"
    Haissam Ziade, Rafic Ayoubi, Raoul Velazco
    2004, v. 1, i. 2, p. 171-186

  • Journal of Electronic Testing, Vol. 19, N.1, February 2003
    Publisher: Springer Science+Business Media B.V., Formerly Kluwer Academic Publishers B.V.
    ISSN: 0923-8174 (Paper) 1573-0727 (Online)
    DOI: 10.1023/A:1021900130241
    Pages: 83 - 90
    "Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied"
    R. Velazco1, S. Rezgui1, TIMA Laboratory, 46 Av. Felix Viallet, 38031 Grenoble, France
    and H. Ziade, Faculty of Engineering I, Lebanese University, Tripoli Lebanon
    Abstract: The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and
    limitations of the studied approach.transient error - fault injection - single event upset - radiation

  • ACIT 2003, AAST
    Haissam Ziade, Rafic Ayoubi, Raoul Velazco, Amer Helwani, Ammar Assoum, Khaled Mechref
    VEU Technique: A New Approach for Simulation-Based Bit-Flip Fault Injection Technique
    http://acit2003.aast.edu/program-day2.html

  • CNRS - Periodicals - LEBANESE SCIENCE JOURNAL VOL.2, NO.1, 2001
    "Extraction des Types d'Evénements dans les Signaux Biomédicaux. Application à l'Electromyogramme Utérin"
    Mohamad Khalil, Jacques Duchêne, Catherine Marque, Haissam Ziade, Lamia Youssef, Samer Hamdache
    Abstract: L'accouchement prématuré, principale cause de morbidité et de mortalité néonatale, demeure un problème majeure en clinique obstétricale. La détection des accouchements prématurés vise au développement d'un système de surveillance des menaces d'accouchement prématuré, basé sur le suivi de la contractilité utérine mesurée au moyen de l'EMG utérin abdominal. Les caractéristiques temporelles et spectrales des bouffées électriques changent au cours du terme. Le but de notre étude est de détecter et classifier les différents types d'événements contenus dans l'EMG utérin à partir des paramètres temporels et spectraux. La détection et la classification des événements sont réalisées en utilisant une méthode séquentielle qui s'appelle méthode de la somme cumulée (CUSUM) et en introduisant la modélisation autoregressive du signal. Les coefficients autoregressifs contiennent des informations sur le contenu fréquentiel des événements. Ils peuvent être utilisés pour réaliser la classification des événements. L'étude de l'efficacité et de la sensibilité de cette méthode se traduit par le test de sa rapidité à donner des résultats pour une utilisation temps réel, son retard à la détection estimé comme étant la différence entre l'instant de détection donné par le programme et le vrai instant de changement observé sur le signal, et enfin le résultat donné par la classification. Une application temps réel a été réalisée en implantant notre algorithme sur un DSP 96002.
    http://www.cnrs.edu.lb/no1-2001abstract.html

  • ...

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